1. Field of the Invention
This invention relates to a process for forming grooves of different types in a semiconductor material, and more particularly to a process for forming grooves of different depths using a single masking step.
2. Description of the Prior Art
The increase in densities of integrated circuits has instigated a trend in isolation technology of using trench or groove formation processes for forming physical gaps between active regions in lieu of the more conventional pn junction and local oxidation (LOCOS.TM.) structures. See, e.g., D. N. K. Wang, et al, "Reactive-Ion Etching Eases Restrictions on Materials and Feature Sizes", Electronics, Nov. 3, 1983, pp. 157,159. Groove isolation is particularly useful in CMOS applications as a method of improving latch-up susceptibility. See, e.g., T. Yamaguchi, et al, "High Speed Latch-up Free 0.5-um Channel CMOS Using Self-Aligned TiSi.sub.2 and Deep-Trench Isolation Technologies", Proceedings IEDM 1983, p. 522. Latch-up can be defined as a state of high excess current accompanied by a low-voltage condition, such that a CMOS device can exhibit parasitic bipolar action, in essence creating a conductive low-impedance path between adjacent devices or substrate areas. Within a well of a CMOS device, a vertical parasitic bipolar device may be formed. In addition, parasitic action can occur laterally between devices within adjacent wells or substrate areas of different conductivity type.
The potential for the occurrence of latch-up increases as circuit density increases (i.e. individual devices are positioned closer together). Conventional techniques for isolating active devices suffer from a density penality which is greatly reduced by the use of grooves for device isolation.
The type of groove necessary to prevent latch-up differs from the type of groove necessary to obtain isolation, specifically with regard to the physical dimensions of the grooves. In particular, a deeper groove is necessary to prevent latch-up between devices in adjacent regions of different conductivity type (sometimes termed wells), while a shallower groove is sufficient to provide isolation between adjacent devices within the same well. Thus, it is ultimately desirable to form grooves of various types on the same integrated circuit.
Since many of the same process steps will be used for forming different types of grooves, it would be desirable to use a single masking step for forming each type of groove.
The use of a single masking step for forming different circuit features is becoming more desirable due to the increasing complexity of devices. When integrated circuits were based on simpler structures one could use separate mask sets for most of the layers in sequence. However, as structures have become progressively more complex it has become necessary to use other means in addition to separate masks to produce structural features. Separate masks and the associated processing steps reduce yield and add to the cost of processing and are therefore to be avoided, if possible.